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differential input, dual, simultaneous sampling, 5 msps, 12-bit, sar adc AD7356 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2011 analog devices, inc. all rights reserved. features dual 12-bit sar adc simultaneous sampling throughput rate: 5 msps per channel specified for v dd at 2.5 v no conversion latency power dissipation: 36 mw at 5 msps on-chip reference: 2.048 v 0.25%, 6 ppm/c dual conversion with read high speed serial interface: spi-/qspi?-/microwire?-/dsp- compatible ?40c to +125c operation available in a 16-lead tssop applications data acquisition systems motion control i and q demodulation functional block diagram sclk AD7356 12-bit successive approximation adc 12-bit successive approximation adc control logic sdata a cs sdata b dgnd refgnd agnd v drive v dd agnd t/h t/h buf buf ref v ina+ v ina? ref a v inb+ v inb? ref b 06505-001 figure 1. general description the AD7356 1 is a dual, 12-bit, high speed, low power, successive approximation adc that operates from a single 2.5 v power supply and features throughput rates up to 5 msps. the part contains two adcs, each preceded by a low noise, wide band- width track-and-hold circuit that can handle input frequencies in excess of 110 mhz. the conversion process and data acquisition use standard control inputs allowing for easy interfacing to microprocessors or dsps. the input signal is sampled on the falling edge of cs ; a conversion is also initiated at this point. the conversion time is determined by the sclk frequency. the AD7356 uses advanced design techniques to achieve very low power dissipation at high throughput rates. with a 2.5 v supply and a 5 msps throughput rate, the part consumes typically 14 ma. the part also offers a flexible power/throughput rate management option. the analog input range for the part is the differential common mode v ref /2. the AD7356 has an on-chip 2.048 v reference that can be overdriven when an external reference is preferred. the AD7356 is available in a 16-lead thin shrink small outline package (tssop). product highlights 1. two complete adc functions. these functions allow simultaneous sampling and conversion of two channels. the conversion result of both channels is simultaneously available on separate data lines or in succession on one data line if only one serial port is available. 2. high throughput with low power consumption. the AD7356 offers a 5 msps throughput rate with 36 mw power consumption. 3. no conversion latency. the AD7356 features two standard successive approx- imation adcs with accurate control of the sampling instant via a cs input and, once off, conversion control. table 1. related devices generic resolution throughput analog input ad7352 12-bit 3 msps differential ad7357 14-bit 4.2msps differential ad7266 12-bit 2 msps differential/single ended ad7866 12-bit 1 msps single-ended ad7366 12-bit 1 msps single-ended bipolar ad7367 14-bit 1 msps single-ended bipolar 1 protected by u.s. patent no. 6,681,332.
important links for the AD7356 * last content update 11/13/2013 03:27 pm similar products & parametric selection tables find similar products by operating parameters low resolution - simultaneous sampling 12-bit pulsar adcs low resolution - muxed 8/10/12/13-bit pulsar adcs for higher resolution see the ad7357 14-bit, 4.25 msps documentation cn-0041: dc-coupled, single-ended-to-differential conversion using the ad8138 low distortion differential adc driver and the AD7356 5 msps, 12-bit sar adc ms-2210: designing power supplies for high speed adc adcs improve equipment accuracy while reducing system size and power consumption analog devices raises the standards in precision data conversion to improve industrial, medical and instrumentation system performance analog devices sets new standard analog-to-digital converter and drivers ics solutions bulletin, volume 10, issue 2 suggested companion products recommended driver amplifiers for the AD7356 for differential, low distortion signals, we recommend the ad8138 or the ada4932-1 . for converting single ended to differential signals using a dual amplifier, we suggest the ad8022 or the ada4932-2 . recommended high accuracy, precision references - 2.5v for the AD7356 for applications requiring the lowest noise performance and output trim adjust, we recommend the adr441 . for high accuracy, low noise, low temperature drift, we recommend the adr431 . for wide supply applications, we recommend the ad780 . for cost sensitive applications, we suggest the ad1582 or the adr391 buffered with the ad8605 or the ad8638 . evaluation kits & symbols & footprints view the evaluation boards and kits page for documentation and purchasing symbols and footprints product recommendations & reference designs cn-0041: dc-coupled, single-ended-to-differential conversion using the ad8138 low distortion differential adc driver and the AD7356 5 msps, 12-bit sar adc design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy AD7356 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
AD7356 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 8 terminology .................................................................................... 10 theory of operation ...................................................................... 12 circuit information.................................................................... 12 converter operation.................................................................. 12 analog input structure.............................................................. 12 analog inputs ............................................................................. 13 driving differential inputs ....................................................... 13 voltage reference ....................................................................... 14 adc transfer function............................................................. 14 modes of operation ....................................................................... 15 normal mode.............................................................................. 15 partial power-down mode ....................................................... 15 full power-down mode ............................................................ 16 power-up times......................................................................... 17 power vs. throughput rate....................................................... 17 serial interface ................................................................................ 18 application hints ........................................................................... 19 grounding and layout .............................................................. 19 evaluating the AD7356 performance ...................................... 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 8/11rev. 0 to rev. a added applications section............................................................ 1 changes to table 1............................................................................ 1 changes to figure 21 and figure 22............................................. 14 added voltage reference section................................................. 14 updated outline dimensions ....................................................... 20 10/08revision 0: initial version
AD7356 rev. a | page 3 of 20 specifications v dd = 2.5 v 10%, v drive = 2.25 v to 3.6 v, internal reference = 2.048 v, f sclk = 80 mhz, f sample = 5 msps, t a = t min to t max 1 , unless otherwise noted. table 2. parameter min typ max unit test conditions/comments dynamic performance f in = 1 mhz sine wave signal-to-noise ratio (snr) 2 70 71.5 db signal-to-(noise and distortion) (sinad) 2 69.5 71 db total harmonic distortion (thd) 2 ?84 ?77.5 db spurious free dynamic range (sfdr) 2 ?85 ?78.5 db intermodulation distortion (imd) 2 fa = 1 mhz + 50 khz, fb = 1 mhz ? 50 khz second-order terms ?84 db third-order terms ?76 db adc-to-adc isolation 2 ?100 db f in = 1 mhz, f noise = 100 khz to 2.5 mhz cmrr 2 ?100 db f noise = 100 khz to 2.5 mhz sample and hold aperture delay 3.5 ns aperture delay match 40 ps aperture jitter 16 ps full power bandwidth @ 3 db 110 mhz @ 0.1 db 77 mhz dc accuracy resolution 12 bits integral nonlinearity (inl) 2 0.5 1 lsb differential nonlinearity (dnl) 2 0.5 0.99 lsb guaranteed no missed codes to 12 bits positive full-scale error 2 1 6 lsb positive full-scale error match 2 2 8 lsb midscale error 2 +5 0/+11 lsb midscale error match 2 2 8 lsb negative full-scale error 2 1 6 lsb negative full-scale error match 2 2 8 lsb analog input fully differential input range (v in+ and v in? ) v cm v ref /2 v v cm = common-mode voltage, v in+ and v in? must remain within gnd and v dd common-mode voltage range 0.5 1.9 v the voltage around which v in+ and v in? are centered dc leakage current 0.5 5 a input capacitance 32 pf when in track mode 8 pf when in hold mode reference input/output v ref input voltage range 2.048 + 0.1 v dd v v ref input current 0.3 0.45 ma when in reference overdrive mode v ref output voltage 2.038 2.058 v 2.048 v 0.5% max @ v dd = 2.5 v 5% 2.043 2.053 v 2.048 v 0.25% max @ v dd = 2.5 v 5% and 25c v ref temperature coefficient 6 20 ppm/c v ref long term stability 100 ppm for 1000 hours v ref thermal hysteresis 2 50 ppm v ref noise 60 v rms v ref output impedance 1
AD7356 rev. a | page 4 of 20 parameter min typ max unit test conditions/comments logic inputs input high voltage (v inh ) 0.6 v drive v input low voltage (v inl ) 0.3 v drive v input current (i in) ) 1 a v in = 0 v or v drive input capacitance (c in ) 3 pf logic outputs output high voltage (v oh ) v drive ? 0.2 v output low voltage (v ol ) 0.2 v floating-state leakage current 1 a floating-state output ca pacitance 5.5 pf output coding straight binary conversion rate conversion time t 2 + 13 t sclk ns track-and-hold acquisition time 2 30 ns full-scale step input, settling to 0.5 lsbs throughput rate 5 msps power requirements 3 v dd 2.25 2.75 v nominal v dd = 2.5 v v drive 2.25 3.6 v i total 4 digital inputs = 0 v or v drive normal mode (operational) 14 20 ma normal mode (static) 6 7.8 ma sclk on or off partial power-down mode 3.5 4.5 ma sclk on or off full power-down mode 5 40 a sclk on or off, ?40c to +85c 90 a sclk on or off, 85c to 125c power dissipation normal mode (operational) 36 59 mw normal mode (static) 16 21.5 mw sclk on or off partial power-down mode 9.5 11.5 mw sclk on or off full power-down mode 16 110 w sclk on or off, ?40c to +85c 250 w sclk on or off, 85c to 125c 1 temperature ranges are as follows: y grade: ?40c to +125c; b grade: ?40c to +85c. 2 see the terminology section. 3 current and power typical specifications are based on results with v dd = 2.5 v and v drive = 3.0 v. 4 i total is the total current flowing in v dd and v drive .
AD7356 rev. a | page 5 of 20 timing specifications v dd = 2.5 v 10%, v drive = 2.25 v to 3.6 v, internal reference = 2.048 v, t a = t max to t min 1 , unless otherwise noted. table 3. parameter limit at t min , t max unit description f sclk 50 khz min 80 mhz max t convert t 2 + 13 t sclk ns max t sclk = 1/f sclk t quiet 5 ns min minimum time between end of serial read and next falling edge of cs t 2 5 ns min cs to sclk setup time t 3 2 6 ns max delay from cs until sdata a and sdata b are three-state disabled t 4 2 , 3 data access time after sclk falling edge 12.5 ns max 1.8 v v drive < 2.25 v 11 ns max 2.25 v v drive < 2.75 v 9.5 ns max 2.75 v v drive < 3.3 v 9 ns max 3.3 v v drive 3.6 v t 5 5 ns min sclk low pulse width t 6 5 ns min sclk high pulse width t 7 2 3.5 ns min sclk to data valid hold time t 8 2 9.5 ns max cs rising edge to sdata , sdata b high impedance a t 9 5 ns min cs rising edge to falling edge pulse width t 10 2 4.5 ns min sclk falling edge to sdata a , sdata b high impedance 9.5 ns max sclk falling edge to sdata a , sdata b high impedance 1 temperature ranges are as follows: y grade: ?40c to +125c; b grade: ?40c to +85c. 2 specified with a load capaci tance of 10 pf on sdata a and sdata b . 3 the time required for the output to cross 0.4 v or 2.4 v.
AD7356 rev. a | page 6 of 20 absolute maximum ratings table 4. parameter rating v dd to agnd, dgnd, refgnd ? 0.3 v to +3 v v drive to agnd, dgnd, refgnd ?0.3 v to +5 v v dd to v drive ?5 v to +3 v agnd to dgnd to refgnd ? 0.3 v to +0.3 v analog input voltages 1 to agnd ? 0.3 v to v dd + 0.3 v digital input voltages 2 to dgnd ?0.3 v to v drive + 0.3 v digital output voltages 3 to dgnd ? 0.3 v to v drive + 0.3 v input current to any pin except supply pins 4 10 ma operating temperature range y grade ? 40c to +125c b grade ? 40c to +85c storage temperature range ? 65c to +150c junction temperature 150c tssop ja thermal impedance 143c/w jc thermal impedance 45c/w lead temperature, soldering reflow temperature (10 sec to 30 sec) 255c esd 1.5 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 analog input voltages are v ina+ , v ina? , v inb+ , v inb? , ref a , and ref b . 2 digital input voltages are cs and sclk. 3 digital output voltages are sdata a and sdata b . 4 transient currents of up to 100 ma do not cause scr latch-up.
AD7356 rev. a | page 7 of 20 pin configuration and fu nction descriptions 1 2 3 4 5 6 7 8 v ina? ref a refgnd v inb? ref b agnd v ina+ v inb+ 16 15 14 13 12 11 10 9 sclk sdata a sdata b cs v dd agnd dgnd v drive AD7356 top view (not to scale) 06505-002 figure 2. pin configuration table 5. pin function descriptions pin no. mnemonic description 1, 2 v ina+ , v ina? analog inputs of adc a. these analog inputs form a fully differential pair. 3, 6 ref a , ref b reference decoupling capacitor pins. decoupling capacitors are connected between these pins and the refgnd pin to decouple the reference buffer for each respective adc. it is recommended to decouple each reference pin with a 10 f capacitor. provided the outp ut is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of the system. the nominal internal reference voltage is 2.048 v and appears at these pins. these pins can also be overdriven by an external reference. the input voltage range for the external reference is 2.048 v + 100 mv to v dd . 4 refgnd reference ground. this is the ground reference point for the reference circuitry on the AD7356. refer any external reference signal to this refgnd voltage. deco upling capacitors must be placed between this pin and the ref a and ref b pins. connect the refgnd pin to the agnd plane of a system. 5, 11 agnd analog ground. this is the ground reference point fo r all analog circuitry on the AD7356. all analog input signals should be referred to this agnd voltage. the agnd and dgnd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 7, 8 v inb? , v inb+ analog inputs of adc b. these analog inputs form a fully differential pair. 9 v dd power supply input. the v dd range for the AD7356 is 2.5 v 10%. decouple the supply to agnd with a 0.1 f capacitor in parallel with a 10 f tantalum capacitor. 10 cs chip select. active low logic input. this input provid es the dual functions of initiating conversions on the AD7356 and framing the serial data transfer. 12 dgnd digital ground. this is the ground reference point for all digital circuitry on the AD7356. connect this pin to the dgnd plane of a system. the dgnd and agnd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 13, 14 sdata b , sdata a serial data outputs. the data output is supplied to each pin as a serial data stream. the bits are clocked out on the falling edge of the sclk input. to access the 12 bits of data from the AD7356, 14 sclk falling edges are required. the data simultaneously appears on both da ta output pins from the simultaneous conversions of both adcs. the data stream consists of two leading zeros followed by the 12 bits of conversion data. the data is provided msb first. if cs is held low for 16 sclk cycles rather th an 14 on the AD7356, then two trailing zeros appear after the 12 bits of data. if cs is held low for a further 16 sclk cycles on either sdata or sdata b , the data from the other adc follows on the sdata pins. this allows data from a simultaneous conversion on both adcs to be gathered in serial format on either sdata a or sdata b . a 15 sclk serial clock. logic input. a serial clock input provides the serial clock for accessing the data from the AD7356. this clock is also used as the clock source for the conversion process. 16 v drive logic power supply input. the voltage supplied at this pin determines at what voltage the interface operates. the voltage at this pin may be different than the voltage at v dd . the v drive supply should be decoupled to dgnd with a 0.1 f capacitor in parallel with a 10 f tantalum capacitor.
AD7356 rev. a | page 8 of 20 typical performance characteristics 0 ?80 ?60 ?40 ?20 ?100 ?120 0 250 500 750 1000 1250 1500 1750 2000 2249 2499 db frequency (khz) 06505-003 16,384 point fft f sample = 5msps f in = 1mhz snr = 71.8db sinad = 71.6db thd = ?83.5db 10,000 20,000 30,000 40,000 50,000 60,000 0 2044 2045 2046 2047 2048 2049 2050 number of occurrences code 06505-005 93 hits 20 hits figure 6. histogram of codes for 65,000 samples figure 3. typical fft 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 0 4000 3500 3000 2500 2000 1500 1000 500 06505-027 code dnl error (lsb) snr (db) analog input frequency (khz) 06505-037 0 65 66 67 68 69 70 71 72 73 1000 2000 3000 4000 5000 figure 7. snr vs. analog input frequency figure 4. typical dnl error psrr (db) supply ripple frequency (mhz) 06505-035 0 ?90 ?85 ?80 ?75 ?70 ?65 ? 60 5 101520 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 0 4000 3500 3000 2500 2000 1500 1000 500 06505-028 code inl error (lsb) 25 figure 8. psrr vs. supply ripple freq uency with no supply decoupling figure 5. typical inl error
AD7356 rev. a | page 9 of 20 0 500 1000 1500 2000 2500 3000 v ref (v) current load (a) 06505-038 2.0460 2.0462 2.0464 2.0466 2.0468 2.0470 2.0472 2.0474 2.0476 2.0478 2.0480 2.0482 figure 9. v ref vs. reference output current drive ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 linearity error (lsb) sclk frequency (mhz) 06505-010 inl max dnl max inl min dnl min figure 10. linearity error vs. sclk frequency ?1.0 ?0.6 ?0.2 0.2 0.6 1.0 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 linearity error (lsb) external v ref (v) 06505-011 inl max dnl max inl min dnl min figure 11. linearity error vs. external v ref 5 6 7 8 9 1 0 1 1 1.82.02.22.42.62.83.03.23.43.6 06505-039 v drive (v) a c c e s s t i m e ( n s ) +125c +85c +25c ?40c figure 12. access time vs. v drive 4 5 6 7 8 9 1.82.02.22.42.62.83.03.23.43.6 06505-040 v drive (v) hold time (ns) +125c +85c +25c ?40c figure 13. hold time vs. v drive
AD7356 rev. a | page 10 of 20 terminology integral nonlinearity (inl) inl is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale (1 lsb below the first code transition) and full scale (1 lsb above the last code transition). differential nonlinearity (dnl) dnl is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. negative full-scale error negative full-scale error is the deviation of the first code transition (00 000) to (00 001) from the ideal (that is, ?v ref + 0.5 lsb) after the midscale error has been adjusted out. negative full-scale error match negative full-scale error match is the difference in negative full- scale error between the two adcs. midscale error midscale error is the deviation of the midscale code transition (011 111) to (100 000) from the ideal (that is, 0 v). midscale error match midscale error match is the difference in midscale error between the two adcs. positive full-scale error positive full-scale error is the deviation of the last code transition (111 110) to (111 111) from the ideal (that is, v ref ? 1.5 lsb) after the midscale error has been adjusted out. positive full-scale error match positive full-scale error match is the difference in positive full- scale error between the two adcs. adc-to-adc isolation adc-to-adc isolation is a measure of the level of crosstalk between adc a and adc b. it is measured by applying a full- scale 1 mhz sine wave signal to one of the two adcs and applying a full-scale signal of variable frequency to the other adc. the adc-to-adc isolation is defined as the ratio of the power of the 1 mhz signal on the converted adc to the power of the noise signal on the other adc that appears in the fft. the noise frequency on the unselected channel varies from 100 khz to 2.5 mhz. power supply rejection ratio (psrr) psrr is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 100 mv p-p sine wave applied to the adc v dd supply of frequency, f s . the frequency of the input varies from 5 khz to 25 mhz. psrr (db) = 10 log(pf / pf s ) where: pf is the power at frequency, f, in the adc output. pf s is the power at frequency, f s , in the adc output. common-mode rejection ratio (cmrr) cmrr is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 100 mv p-p sine wave applied to the common-mode voltage of v in+ and v in? of frequency, f s . cmrr (db) = 10 log( pf/pf s ) where: pf is the power at frequency (f) in the adc output. pf s is the power at frequency (f s ) in the adc output. track-and-hold acquisition time the track-and-hold amplifier returns to track mode at the end of a conversion. the track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 0.5 lsb, after the end of a conversion. signal-to-(noise and distortion) ratio (sinad) sinad is the measured ratio of signal-to-(noise and distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitiza- tion process; the more levels, the smaller the quantization noise. the theoretical sinad for an ideal n-bit converter with a sine wave input is given by sinad = (6.02 n + 1.76) db thus, for a 12-bit converter, sinad is 74 db and for a 14-bit converter, sinad is 86 db.
AD7356 rev. a | page 11 of 20 total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental. for the AD7356, it is defined as () 1 65432 v vvvvv thd 22222 log20db ++++ ?= where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. spurious free dynamic range (sfdr) sfdr is the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is a noise peak. intermodulation distortion (imd) with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n is equal to zero. for example, the second-order terms include (fa + fb) and (fa ? fb), while the third-order terms include ( 2 fa + fb), ( 2 fa ? fb), (fa + 2 fb), and (fa ? 2fb). the AD7356 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second-order terms are usually distanced in frequency from the original sine waves and the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. thermal hysteresis thermal hysteresis is defined as the absolute maximum change of reference output voltage after the device is cycled through temperature from either t_hys+ = +25c to t max to +25c t_hysC = +25c to t min to +25c thermal hysteresis is expressed in ppm using the following equation: 6 10 )25( )_()25( )ppm( ? = cv hystvcv v ref ref ref hys where: v ref (25 c ) is v ref at 25c. v ref (t_hys) is the maximum change of v ref at t_hys+ or t_hysC.
AD7356 rev. a | page 12 of 20 theory of operation circuit information the AD7356 is a high speed, dual, 12-bit, single-supply, succes- sive approximation analog-to-digital converter (adc). the part operates from a 2.5 v power supply and features throughput rates of up to 5 msps. the AD7356 contains two on-chip differential track-and-hold amplifiers, two successive approximation adcs, and a serial interface with two separate data output pins. the part is housed in a 16-lead tssop, offering the user considerable space-saving advantages over alternative solutions. the serial clock input accesses data from the part but also provides the clock source for each successive approximation adc. the AD7356 has an on-chip 2.048 v reference. if an external reference is desired the internal reference can be overdriven with a reference value ranging from (2.048 v + 100 mv) to v dd . if the internal reference is to be used elsewhere in the system, then the reference output needs to be buffered first. the differential analog input range for the AD7356 is v cm v ref /2. the AD7356 features power-down options to allow power saving between conversions. the power-down feature is implemented via the standard serial interface, as described in the modes of operation section. converter operation the AD7356 has two successive approximation adcs, each based around two capacitive dacs. figure 14 and figure 15 show simplified schematics of one of these adcs in acquisition and conversion phase. the adc comprises a control logic, a sar, and two capacitive dacs. in figure 14 (the acquisition phase), sw3 is closed, sw1 and sw2 are in position a, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. capacitive dac capacitive dac control logic comparator sw3 sw1 a a b b sw2 c s c s v in+ v in? v ref 06505-012 figure 14. adc acquisition phase when the adc starts a conversion (see figure 15 ), sw3 opens and sw1 and sw2 move to position b, causing the comparator to become unbalanced. both inputs are disconnected once the conversion begins. the control logic and charge redistribution dacs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. the output impedances of the sources driving the v in+ and v in? pins must be matched; otherwise, the two inputs may have different settling times, resulting in errors. capacitive dac capacitive dac control logic comparator sw3 sw1 a a b b sw2 c s c s v in+ v in? v ref 06505-013 figure 15. adc conversion phase analog input structure figure 16 shows the equivalent circuit of the analog input structure of the AD7356. the four diodes provide esd protection for the analog inputs. care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mv. this causes these diodes to become forward biased and start conducting into the substrate. these diodes can conduct up to 10 ma without causing irreversible damage to the part. the c1 capacitors in figure 16 are typically 8 pf and can primarily be attributed to pin capacitance. the r1 resistors are lumped components made up of the on resistance of the switches. the value of these resistors is typically about 30 . the c2 capacitors are the sampling capacitors of the adc with a capacitance of 32 pf typically. v dd c1 d d v in+ r1 c2 v dd c1 d d v in? r1 c2 06505-015 figure 16. equivalent analog input circuit, conversion phaseCswitches open, track phaseswitches closed
AD7356 rev. a | page 13 of 20 for ac applications, removing high frequency components from the analog input signal is recommended by the use of an rc low-pass filter on the analog input pins. in applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances significantly affect the ac perfor- mance of the adc and may necessitate the use of an input buffer amplifier. the choice of the op amp is a function of the particular application. when no amplifier is used to drive the analog input, limit the source impedance to low values. the maximum source impedance depends on the amount of thd that can be tolerated. thd increases as the source impedance increases and performance degrades. figure 17 shows a graph of the thd vs. the analog input signal frequency for different source impedances. ?87 ?85 ?83 ?81 ?79 ?77 ?75 ?73 ?71 ?69 ?67 ? 65 100 200 1000 1500 2000 2500 thd (db) frequency (khz) 06505-026 100 ? 50? 33? 10? figure 17. thd vs. analog input signal frequency for various source impedances figure 18 shows a graph of the thd vs. the analog input frequency while sampling at 5 msps. in this case, the source impedance is 33 . ?90 ?86 ?82 ?78 ?74 ?70 ? 66 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 thd (db) analog input frequency (khz) 07044-029 figure 18. thd vs. analog input frequency analog inputs differential signals have some benefits over single-ended signals, including noise immunity based on the devices common-mode rejection and improvements in distortion performance. figure 19 defines the fully differential input of the AD7356. v in+ AD7356* v in? v ref p-p v ref p-p * additional pins omitted for clarity. common-mode voltage 06505-034 figure 19. differential input definition the amplitude of the differential signal is the difference between the signals applied to the v in+ and v in? pins in each differential pair (v in+ ? v in? ). v in+ and v in? should be simultaneously driven by two signals each of amplitude (v ref ) that are 180 out of phase. this amplitude of the differential signal is, therefore, Cv ref to +v ref peak-to-peak regardless of the common mode (cm). cm is the average of the two signals and is, therefore, the voltage on which the two inputs are centered. cm = ( v in+ + v in? )/2 this results in the span of each input being cm v ref /2. this voltage has to be set up externally. when setting up the cm, ensure that v in+ and v in? remain within gnd/v dd . when a conversion takes place, cm is rejected, resulting in a virtually noise-free signal of amplitude, Cv ref to +v ref , corresponding to the digital codes of 0 to 4095 for the AD7356. driving differential inputs differential operation requires v in+ and v in? to be driven simultaneously with two equal signals that are 180 out of phase. because not all applications have a signal preconditioned for differential operation, there is often a need to perform a single- ended-to-differential conversion. differential amplifier an ideal method of applying differential drive to the AD7356 is to use a differential amplifier such as the ad8138 . this part can be used as a single-ended-to-differential amplifier or as a differential-to-differential amplifier. the ad8138 also provides common-mode level shifting. figure 20 shows how the ad8138 can be used as a single-ended-to-differential amplifier. the positive and negative outputs of the ad8138 are connected to the respective inputs on the adc via a pair of series resistors to minimize the effects of switched capacitance on the front end of the adc. the architecture of the ad8138 results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components.
AD7356 rev. a | page 14 of 20 06505-033 gnd 2 v ref p-p 27 ? 27 ? v+ v? v+ v? 1.024v 2.048v 0v 1.024v 2.048v 0v ref a /ref b v in+ AD7356* v in? 220 ? 10f *additional pins omitted for clarity. 220 ? 220 ? 20k ? a 440 ? 10k ? 220 ? 06505-031 +2.048v gnd ?2.048v ad8138 r g 1 r s * r s * r g 2 r f 2 v ocm r f 1 2.048v v in+ v in? 1.024v 0v 2.048v 1.024v 0v AD7356 c f 2 c f 1 10k? 10k? 10f ref a /ref b *mount as close to the AD7356 as possible and ensure that high precision r s resistors are used. r s ? 33 ? ; r g 1 = r f 1 = r f 2 = 499 ? ; c f 1 = c f 2 = 39pf; r g 2 = 523 ? 51? figure 22. dual op amp circuit to convert a single-ended bipolar signal into a differential unipolar signal voltage reference figure 20. using the ad8138 as a single-ended-to-differential amplifier the AD7356 allows the choice of a very low temperature drift internal voltage reference or an external reference. the internal 2.048 v reference of the AD7356 provides excellent perfor- mance and can be used in almost all applications. when the internal reference is used, the reference voltage is present on the ref a and ref b pins. these pins should be decoupled to refgnd with 10 f capacitors. the internal reference voltage can be used elsewhere in the system, provided it is buffered externally. if the analog inputs source being used has zero impedance, all four resistors (r g 1, r g 2, r f 1, and r f 2) should be the same value as each other. if the source has a 50 impedance and a 50 termination, for example, increase the value of r g 2 by 25 to balance this parallel impedance on the input and thus ensure that both the positive and negative analog inputs have the same gain. the outputs of the amplifier are perfectly matched balanced differential outputs of identical amplitude, and are exactly 180 out of phase. the ref a and ref b pins can also be overdriven with an external voltage reference if desired. the applied reference voltage can range from 2.048 v + 100 mv to v dd . a common cho ice would be to use an external 2.5 v reference such as the adr441 or adr431 . op amp pair an op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the AD7356. the circuit configurations shown in figure 21 and figure 22 show how an op amp pair can be used to convert a single-ended signal into a differential signal for a bipolar and unipolar input signal, respectively. adc transfer function the output coding for the AD7356 is straight binary. the designed code transitions occur at successive lsb values (1 lsb, 2 lsbs, and so on). the lsb size is (2 v ref )/4096. the ideal transfer characteristic of the AD7356 is shown in figure 23 . the voltage applied to point a sets up the common-mode voltage. in both diagrams, it is connected in some way to the reference. the ad8022 is a suitable dual op amp that could be used in this configuration to provide differential drive to the AD7356. 000 ... 000 000 ... 001 000 ... 010 111 ... 101 111 ... 110 111 ... 111 adc code analog input ?v ref + 0.5 lsb ?v ref + 1 lsb +v ref ? 1.5 lsb +v ref ? 1 lsb 06505-014 06505-032 gnd v ref p-p 27 ? 27 ? v+ v? v+ v? 1.024v 2.048 v 0v 1.024v 2.048v 0v ref a /ref b v in+ AD7356* v in? 220 ? 10f *additional pins omitted for clarity. 220 ? 220 ? 10k ? 10k ? a 220 ? v ref 2 figure 21. dual op amp circuit to convert a single-ended unipolar signal into a differential signal figure 23. AD7356 ideal transfer characteristic
AD7356 rev. a | page 15 of 20 modes of operation the mode of operation of the AD7356 is selected by controlling the logic state of the cs signal during a conversion. there are three possible modes of operation: normal mode, partial power- down mode, and full power-down mode. after a conversion is initiated, the point at which cs is pulled high determines which power-down mode, if any, the device enters. similarly, if already in a power-down mode, cs can control whether the device returns to normal operation or remains in a power-down mode. these modes of operation are designed to provide flexible power management options. these options can be chosen to optimize the power dissipation/throughput rate ratio for the differing application requirements. normal mode normal mode is intended for applications needing the fastest throughput rates because the user does not have to worry about any power-up times because the AD7356 remains fully powered at all times. figure 24 shows the general diagram of the operation of the AD7356 in normal mode. sclk leading zeros + conversion result cs sdat a a sdat a b 1 10 1 4 06505-018 figure 24. normal mode operation the conversion is initiated on the falling edge of cs , as described in the section. to ensure that the part remains fully powered up at all times, serial interface cs must remain low until at least 10 sclk falling edges have elapsed after the falling edge of cs . if cs is brought high any time after the 10 th sclk falling edge but before the 14 th sclk falling edge, the part remains powered up; however, the conversion is terminated and sdata and sdata b go back into three-state. to complete the conversion and access the conversion result for the AD7356, 14 serial clock cycles are required. the sdata lines do not return to three- state after 14 sclk cycles have elapsed but instead do so when a cs is brought high again. if cs is left low for another two sclk cycles, two trailing zeros are clocked out after the data. if cs is left low for a further 14 sclk cycles, the result for the other adc on board is also accessed on the same sdata line (see and the section). figure 31 serial interface once 32 sclk cycles have elapsed, the sdata line returns to three-state on the 32 nd sclk falling edge. if cs is brought high prior to this, the sdata line returns to three-state at that point. thus, cs may idle low after 32 sclk cycles until it is brought high again sometime prior to the next conversion. the bus still returns to three-state upon completion of the dual result read. when a data transfer is complete and sdata a and sdata b have returned to three-state, another conversion can be initiated after the quiet time, t quiet , has elapsed by bringing cs low again (assuming the required acquisition time has been allowed). partial power-down mode partial power-down mode is intended for use in applications in which slower throughput rates are required. either the adc is powered down between each conversion or a series of conversions can be performed at a high throughput rate and the adc is then powered down between these bursts of several conversions. it is recommended that the AD7356 not remain in partial power-down mode for longer than 100 s. when the AD7356 is in partial power-down, all analog circuitry is powered down except for the on-chip reference and reference buffers. to enter partial power-down mode, the conversion process must be interrupted by bringing cs high any time after the second falling edge of sclk and before the 10 th falling edge of sclk, as shown in . when figure 25 cs has been brought high in this window of sclks, the part enters partial power-down, the conversion that was initiated by the falling edge of cs is terminated, and sdata a and sdata b go back into three-state. if cs is brought high before the second sclk falling edge, the part remains in normal mode and does not power down. this avoids accidental power-down due to glitches on the cs line. sclk three-state cs sdata a sdata b 11 10 4 2 06505-019 figure 25. entering partial power-down mode to exit this mode of operation and power up the AD7356 again, perform a dummy conversion. on the falling edge of cs , the device begins to power up, and continues to power up as long as cs is held low until after the falling edge of the 10 th sclk. the device is fully powered up after approximately 200 ns have elapsed (or one full conversion) and valid data results from the next conversion, as shown in . if figure 26 cs is brought high before the second falling edge of sclk, the AD7356 again goes into partial power-down. this avoids accidental power-up due to glitches on the cs line. although the device may begin to power up on the falling edge of cs , it powers down again on the rising edge of cs . if the AD7356 is already in partial power-down mode and cs is brought high between the second and 10 th falling edges of sclk, the device enters full power-down mode.
AD7356 rev. a | page 16 of 20 full power-down mode full power-down mode is intended for use in applications where throughput rates slower than those in partial power- down mode are required because power-up from a full power- down takes substantially longer than that from a partial power- down. this mode is more suited to applications in which a series of conversions performed at a relatively high throughput rate are followed by a long period of inactivity and, thus, power- down. when the AD7356 is in full power-down mode, all analog circuitry is powered down including the on-chip reference and reference buffers. full power-down mode is entered in a similar way as partial power-down mode, except that the timing sequence shown in figure 25 must be executed twice. the conversion process must be interrupted in a similar fashion by bringing cs high anywhere after the second falling edge of sclk and before the 10 th falling edge of sclk. the device enters partial power-down mode at this point. to reach full power-down, the next conversion cycle must be interrupted in the same way, as shown in figure 27 . when cs is brought high in this window of sclks, the part fully powers down. note that it is not necessary to complete the 14 or 16 sclks once cs has been brought high to enter a power-down mode. to exit full power-down mode and power-up the AD7356, perform a dummy conversion, similar to powering up from partial power-down. on the falling edge of cs , the device begins to power up as long as cs is held low until after the falling edge of the 10 th sclk. the required power-up time must elapse before a conversion can be initiated, as shown in . figure 28 sclk cs sdata a sdata b invalid data valid data 11 0 1 4 1 4 1 the part begins to power up. t power-up1 06505-020 the part is fully powered up; see the power-up times section. figure 26. exiting partial power-down mode three-state 11 0 1 4 2 sclk cs s dat a a s dat a b three-state 11 0 2 invalid data invalid data the part begins to power up. the part enters partial power-down mode. the part enters full power-down mode. 1 4 06505-021 figure 27. entering full power-down mode sclk sdata a sdata b invalid data valid data 1 10 14 14 1 the part begins to power up. the part is fully powered up; see the power-up times section. t power-up2 cs 06505-022 figure 28. exiting full power-down mode
AD7356 rev. a | page 17 of 20 power-up times the AD7356 has two power-down modes: partial power-down and full power-down, which are described in detail in the normal mode , partial power-down mode , and full power-down mode sections. this section deals with the power-up time required when coming out of any of these modes. note that the recom- mended decoupling capacitors must be in place on the ref a and ref b pins for the power-up times to apply. to power up from partial power-down mode, one dummy cycle is required. the device is fully powered up after approximately 200 ns have elapsed from the falling edge of cs . when the partial power-up time has elapsed, the adc is fully powered up, and the input signal is acquired properly. the quiet time, t quiet , must still be allowed from the point where the bus goes back into three-state after the dummy conversion to the next falling edge of cs . to power up from full power-down mode, approximately 6 ms should be allowed from the falling edge of cs , shown in as t power-up2 . figure 28 note that during power-up from partial power-down mode, the track-and-hold, which is in hold mode while the part is powered down, returns to track mode after the first sclk edge that the part receives after the falling edge of cs . when power supplies are first applied to the AD7356, the adc can power up in either of the power-down modes or in normal mode. because of this, it is best to allow a dummy cycle to elapse to ensure that the part is fully powered up before attempting a valid conversion. likewise, if the part is to be kept in partial power-down mode immediately after the supplies are applied, then two dummy cycles must be initiated. the first dummy cycle must hold cs low until after the 10 th sclk falling edge; in the second cycle, cs must be brought high between the second and 10 th sclk falling edges (see ). figure 25 alternatively, if the part is to be placed into full power-down mode when the supplies are applied, three dummy cycles must be initiated. the first dummy cycle must hold cs low until after the 10 th sclk falling edge; the second and third dummy cycles place the part into full power-down mode (see and the section). figure 27 modes of operation power vs. throughput rate the power consumption of the AD7356 varies with the throughput rate. when using very slow throughput rates and as fast an sclk frequency as possible, the various power- down options can be used to make significant power savings. however, the AD7356 quiescent current is low enough that even without using the power-down options, there is a noticeable variation in power consumption with sampling rate. this is true whether a fixed sclk value is used or it is scaled with the sampling rate. figure 29 shows a plot of power vs. throughput rate when operating in normal mode for a fixed maximum sclk frequency and a sclk frequency that scales with the sampling rate. the internal reference was used for figure 29 . 10 14 18 22 26 30 34 38 0 1000 2000 5000 3000 4000 power (mw) throughput (ksps) 06505-030 80mhz sclk variable sclk figure 29. power vs. throughput rate
AD7356 rev. a | page 18 of 20 serial interface figure 30 shows the detailed timing diagram for serial interfacing to the AD7356. the serial clock provides the conversion clock and controls the transfer of information from the AD7356 during conversion. the cs signal initiates the data transfer and conversion process. the falling edge of cs puts the track and hold into hold mode, at which point the analog input is sampled and the bus is taken out of three-state. the conversion is also initiated at this point and requires a minimum of 14 sclks to complete. once 13 sclk falling edges have elapsed, the track and hold goes back into track on the next sclk rising edge, as shown in at point b. if a 16-bit data transfer is used on the AD7356, then two trailing zeros appear after the final lsb. on the rising edge of figure 30 cs , the conversion is terminated and sdata a and sdata b go back into three-state. if cs is not brought high, but is instead held low for an additional 14 sclk cycles, the data from the conversion on adc b is output on sdata a (see ). likewise, the data from the conversion on adc a is output on sdata b . in this case, the sdata line in use goes back into three-state on the 32 nd sclk falling edge or the rising edge of figure 31 cs , whichever occurs first. a minimum of 14 serial clock cycles is required to perform the conversion process and to access data from one conversion on either data line of the AD7356. cs falling low provides the leading zero to be read in by the microcontroller or dsp. the remaining data is then clocked out by subsequent sclk falling edges, beginning with a second leading zero. thus, the first falling clock edge on the serial clock has the leading zero provided and also clocks out the second leading zero. the 12-bit result then follows with the final bit in the data transfer and is valid on the 14 th falling edge (having been clocked out on the previous (13 th ) falling edge). in applications with a slower sclk, it may be possible to read in data on each sclk rising edge depending on the sclk frequency. with a slower sclk, the first rising edge, of sclk after the cs falling edge has the second leading zero provided, and the 13 th rising sclk edge has db0 provided. cs sclk 1 5 13 sdata a sdata b 2 leading zeros three- state t 4 2 34 t 5 t 3 t quiet t 2 three-state db11 db10 db2 db0 t 6 t 7 t 8 00 db1 db9 db8 t 9 t acquisition t convert 06505-024 b figure 30. serial interface timing diagram cs sclk 1 5 15 sdata a three- state t 4 2 34 16 t 5 t 3 t 2 three- state t 6 t 7 14 00 zero db11 b 17 2 leading zeros t 10 32 db11 a 2 leading zeros db10 a db9 a zero zero zero 2 trailing zeros zero zero 2 trailing zeros 06505-025 figure 31. reading data from both adcs on one sdata line with 32 sclks
AD7356 rev. a | page 19 of 20 application hints grounding and layout the analog and digital supplies to the AD7356 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the printed circuit board (pcb) that houses the AD7356 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this design facilitates the use of ground planes that can be easily separated. to provide optimum shielding for ground planes, a minimum etch technique is generally best. the two agnd pins of the AD7356 should be sunk in the agnd plane. the refgnd pin should also be sunk in the agnd plane. digital and analog ground planes should be joined in only one place. if the AD7356 is in a system in which multiple devices require an agnd and dgnd connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the ground pins on the AD7356. avoid running digital lines under the device because this couples noise onto the die. allow the analog ground planes to run under the AD7356 to avoid noise coupling. the power supply lines to the AD7356 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. to avoid radiating noise to other sections of the board, shield fast switching signals such as clocks, with digital ground; and never run clock signals near the analog inputs. avoid crossover of digital and analog signals. to reduce the effects of feed- through within the board, traces on opposite sides of the board should run at right angles to each other. a microstrip technique is the best method but is not always possible with a double sided board. in this technique, the component side of the board is dedicated to ground planes and signals are placed on the solder side. good decoupling is important; decouple all supplies with 10 f tantalum capacitors in parallel with 0.1 f capacitors to gnd. to achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. the 0.1 f capacitor, (including the common ceramic types or surface-mount types) should have low effective series resistance (esr) and effective series induc- tance (esi). these low esr and esi capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to logic switching. evaluating the AD7356 performance the recommended layout for the AD7356 is outlined in the evaluation board documentation. the evaluation board package includes a fully assembled and tested evaluation board, docu- mentation, and software for controlling the board from the pc via the converter evaluation and development board (ced). the ced can be used in conjunction with the AD7356 eval- uation board (as well as many other evaluation boards ending in the ed designator from analog devices, inc.) to demonstrate/ evaluate the ac and dc performance of the AD7356. the software allows the user to perform ac (fast fourier transform) and dc (linearity) tests on the AD7356. the software and docu- mentation are on a cd shipped with the evaluation board.
AD7356 rev. a | page 20 of 20 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 32. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters ordering guide model 1 notes temperature range package description package option AD7356bruz ?40c to +85c 16-lead tssop ru-16 AD7356bruz-500rl7 ?40c to +85c 16-lead tssop ru-16 AD7356bruz-rl ?40c to +85c 16-lead tssop ru-16 AD7356yruz ?40c to +125c 16-lead tssop ru-16 AD7356yruz-500rl7 ?40c to +125c 16-lead tssop ru-16 AD7356yruz-rl ?40c to +125c 16-lead tssop ru-16 eval-AD7356edz 2 evaluation board eval-ced1z 3 converter evaluation and development board 1 z = rohs compliant part. 2 this evaluation board can be used as a standalone evaluation board or in conjunction with the eval-ced1z board for evaluation/ demonstration purposes. 3 this evaluation board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards en ding in the ed designator. ?2008C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06505-0-8/11(a)

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